Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory element, such as a flash memory unit. In this regard, one conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric element that is capable of storing two bits of data. In such an arrangement, one bit can be stored using a first charge storing region on one side of the charge trapping dielectric element, while a second bit can be stored using a second charge storing region on the other side of the charge trapping dielectric element.
FIG. 1 is a cross sectional view of a conventional dual bit memory cell 100. Memory cell 100 includes a silicon nitride layer 102 and a P-type semiconductor substrate 104 having a first buried junction region 106 and a second buried junction region 108. First buried junction region 106 and second buried junction region 108 are each formed from an N+ semiconductor material. Silicon nitride layer 102 is sandwiched between two layers of silicon oxide (identified by reference numbers 110 and 112).
Overlying silicon oxide layer 110 is a polysilicon gate 114. Gate 114 is doped with an N-type impurity (e.g., phosphorus). Memory cell 100 is capable of storing two data bits: a left bit represented by the dashed circle 116; and a right bit represented by the dashed circle 118. In practice, memory cell 100 is generally symmetrical and first buried junction region 106 and second buried junction region 108 are interchangeable. In this regard, first buried junction region 106 may serve as the source region with respect to the right bit 118, while second buried junction region 108 may serve as the drain region with respect to the right bit 118. Conversely, second buried junction region 108 may serve as the source region with respect to the left bit 116, while first buried junction region 106 may serve as the drain region with respect to the left bit 116.
FIG. 2 is a simplified diagram of a plurality of dual bit memory cells arranged in accordance with a conventional virtual ground array architecture 200 (a practical array architecture can include thousands of dual bit memory cells). Array architecture 200 includes a number of buried bitlines formed in a semiconductor substrate as mentioned above. FIG. 2 depicts three buried bit lines (reference numbers 202, 204, and 206), each being capable of functioning as a drain or a source for memory cells in array architecture 200. Array architecture 200 also includes a number of wordlines that are utilized to control the gate voltage of the memory cells. FIG. 2 depicts four wordlines (reference numbers 208, 210, 212, and 214) that generally form an orthogonal pattern with the bitlines. Although not shown in FIG. 2, charge trapping dielectric material is sandwiched in the junctions between the bitlines and the wordlines. The dashed lines in FIG. 2 represent two of the dual bit memory cells in array architecture 200: a first cell 216 and a second cell 218. Notably, bitline 204 is shared by first cell 216 and second cell 218. Array architecture 200 is known as a virtual ground architecture because ground potential can be applied to any selected bitline and there need not be any bitlines with a fixed ground potential.
Control logic and circuitry for array architecture 200 governs the selection of memory cells, the application of voltage to the wordlines, and the application of voltage to the bitlines during conventional flash memory operations, such as: programming; reading; erasing; and soft programming. Voltage is delivered to the bitlines using conductive metal lines and bitline contacts. FIG. 2 depicts three conductive metal lines (reference numbers 220, 222, and 224) and three bitline contacts (reference numbers 226, 228, and 230). For a given bitline, a bitline contact is used once every 16 wordlines because the resistance of the bitlines is very high.
Programming of memory cell 100 can be accomplished by known hot electron injection techniques (also known as channel hot electron or CHE programming). In accordance with conventional programming techniques, the right bit 118 is programmed by applying a relatively high programming voltage to gate 114 via the appropriately selected wordline, grounding the bitline corresponding to first buried junction region 106 (which serves as the source in this case), and applying a relatively high drain bias voltage to the bitline corresponding to second buried junction region 108 (which serves as the drain in this case). Conversely, the left bit 116 is programmed by applying a relatively high programming voltage to gate 114 via the appropriately selected wordline, grounding the bitline corresponding to second buried junction region 108 (which serves as the source in this case), and applying a relatively high drain bias voltage to the bitline corresponding to first buried junction region 106 (which serves as the drain in this case).
Referring again to FIG. 2, conventional CHE programming of a flash memory array arranged in a virtual ground architecture may result in excessive current leakage flowing under the unselected wordlines, between the wordlines, and in the bitline contact areas, and, hence, excessive power consumption. Such bitline leakage current can increase the required programming current by tens of microamperes, which is a significant amount considering the nominal operating characteristics of such a flash memory array. Moreover, due to natural degradation of the cells, the amount of this parasitic leakage current can increase by roughly up to two orders of magnitude (100×) after the array has experienced many program-erase cycles. Excessive leakage current can be very undesirable in low power applications such as portable electronic devices, wireless telephones, or the like. Excessive leakage current may have other negative implications in a practical flash memory device, such as an undesirable reduction of the voltage delivered to the drain of the cell during the programming operation.
Bitline leakage current can also occur during conventional verification operations for a virtual ground architecture soft program verify, erase verify, and program verify. Such verification operations are similar to the programming operations mentioned above; however, lower wordline voltages and lower drain bias voltages are applied. The goal of such verification operations is to determine whether the threshold voltage (VT) of the target memory cell is within a desired range corresponding to an acceptable erase state or an acceptable program state, depending upon the particular verification operation. Regardless of the particular VT being verified, the verification operation generates a very low verification current in the target memory cell and compares the verification current to a reference current generated by a reference memory cell. Bitline leakage current, even in small amounts, can introduce errors in the verification operation because the measurement circuitry measures the actual verification current combined with any leakage current.
Accordingly, it is desirable to control, reduce, or eliminate leakage current during programming of memory cells in a virtual ground architecture. In addition, it is desirable to control, reduce, or eliminate the leakage current component during verification operations of memory cells in a virtual ground architecture. Furthermore, other desirable features and characteristics of embodiments of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.